`timescale 1ns/1ns
module s_to_p(
    input              clk        ,   
    input              rst_n       ,
    input               valid_a     ,
    input              data_a      ,
  
   output  reg        ready_a     ,
   output  reg         valid_b     ,
    output  reg [5:0]   data_b
);
reg    [5:0]       data_reg;
reg    [2:0]       data_cnt;
 
always @(posedge clk or negedge rst_n ) begin//ready_a信号准备
    if(!rst_n) 
        ready_a <= 'd0;
    else 
        ready_a <= 1'd1;
end
always @(posedge clk or negedge rst_n ) begin//接收数据计数器
    if(!rst_n) 
        data_cnt <= 'd0;
    else if(valid_a && ready_a)
        data_cnt <= (data_cnt == 3'd5) ? 'd0 : (data_cnt + 1'd1);
end
always @(posedge clk or negedge rst_n ) begin//接收数据缓存
    if(!rst_n) 
        data_reg <= 'd0;
    else if(valid_a && ready_a)
        data_reg <= {data_a, data_reg[5:1]};
end
 
always @(posedge clk or negedge rst_n ) begin//结果输出
    if(!rst_n)begin
        valid_b <= 'd0;
        data_b <= 'd0;
    end 
    else if(data_cnt == 3'd5)begin
        valid_b <= 1'd1;
        data_b <= {data_a, data_reg[5:1]};
    end
    else
        valid_b <= 'd0;
end
endmodule